Building an Op-Amp from Silicon Up: Designing and Testing a Custom Chip with Open-Source Tools
イチケン / ICHIKEN
Electronics creator Ichiken has previously built an operational amplifier out of discrete transistor components. In this video they take the same idea much further: they design an op-amp at the transistor level, lay it out on a silicon chip, have it fabricated at a semiconductor foundry, and then test the chip on the bench. The video covers two things. The first is how an individual hobbyist got through the design, layout, and fabrication process with open-source tools and community support. The second is how well the resulting op-amp actually performs.
Timeline and Community Support
Design work began around June 2025, and the deadline for submitting design data was in early August. Ichiken says this meant learning op-amp design methodology, the design software, and semiconductor layout "at a fairly rapid pace." They credit the ISHI-kai (ISHI Association), an open-source semiconductor community, with a great deal of help throughout the project. They point viewers to the video description for materials on the group's activities and on semiconductor design methods. Because the full project covered too much to show in one video, Ichiken presents only the parts they consider most important.
The Design Flow and the Open-Source Toolchain
Ichiken describes the basic flow as four steps: draw a schematic, simulate it, create the layout, and verify the layout. They compare this to ordinary electronic circuit design. In their view, anyone who has used the circuit simulator LTspice or drawn a circuit in the PCB CAD program KiCad could manage a simple op-amp's circuit design and layout. The main hurdle is learning the specific software, and parts of it can be somewhat difficult. For newcomers, Ichiken suggests starting with a logic NOT circuit (an inverter), which they think will help people keep up with the process.
Commercial semiconductor design software is generally expensive. Ichiken stresses that open-source simulators and layout tools can be used for free, and that volunteers have packaged them so the software is easy to set up. Semiconductor design also requires a Process Design Kit (PDK), and one is available as well. Ichiken says they are grateful that the whole environment can be put together easily. Setup procedures are linked in the description.
More Design Freedom, More Difficulty
Ichiken contrasts discrete design with transistor-level design. When you build with discrete semiconductors, each component's performance is fixed, and you make adjustments with external resistors and similar parts. In transistor-level design, you set the performance of each transistor yourself, which gives you much more design freedom.
That freedom sounds appealing, but for a beginner like themselves Ichiken says it makes things harder, because they didn't know what values to choose for transistor performance. They settled on approximate values with a lot of guidance from ISHI-kai members. They add that a viewer could probably do something similar by following the PDF documents linked in the description.
The chip was designed in a CMOS process, and Ichiken highlights one consequence. PMOS transistors perform worse than NMOS, so a PMOS device needs roughly twice the area of an NMOS device to reach the same performance. This shows up later in the layout. With discrete components you can simply use a complementary pair, and Ichiken says there are few situations where you have to think much about that performance gap. When you design from a lower layer, as in this project, it becomes something you must account for.
Circuit Structure and Test Benches
The finished schematic divides into blocks: an input differential amplifier stage, an output stage, and a reference current source. Ichiken's process was to split the circuit into small blocks and build a test bench for each one. Once every block worked on its own, they combined everything and simulated the whole circuit to confirm it worked without problems. Only then did they move on to transistor layout.
Layout Techniques
Ichiken found transistor layout "very deep," something they only realized while doing this project. The finished layout contains the input differential amplifier, the reference current source, the phase-compensation circuitry, and the output circuit. They admit that a quick glance at it doesn't reveal much, even though they worked hard on it. They then walk through several techniques they used.
Common centroid. The transistors in the differential amplifier are arranged point-symmetrically. For FETs used in pairs, as in a differential amplifier, this layout technique keeps temperature differences from arising between transistors A and B, which Ichiken says gives better temperature characteristics.
Dummy polysilicon. Ichiken explains that during manufacturing, the silicon at the edges apparently gets scraped away. If this happens to a working transistor, the circuit drifts from its designed characteristics. To prevent this, extra transistors that do not contribute to circuit operation are placed at the ends, which protects the transistors that do affect the internal circuit.
Double vias and double contacts. Vias and contacts have high resistance compared with wiring, so using several of them in parallel lowers resistance. Because these structures are extremely fine, a single via or contact may also fail because of a manufacturing defect. Multiple vias and contacts let the circuit keep working if one fails. Ichiken notes this is the same idea as using multiple vias on a printed circuit board to reduce resistance.
Wider current-carrying traces. Wiring that carries current was made thicker throughout.
Verification and Where the Time Went
After layout, the design must be checked in two ways: the layout has to match the schematic, and it must not violate any design rules. If the layout is wrong or breaks a rule, Ichiken warns, you may have to delete work that took a long time and start over. They call this quite a time-consuming process. Circuit design itself did not take long. Layout and verification took the most time, which they estimate at about 30 hours.
Fabrication Through a Shuttle Service
The finished data went to a foundry, in this case Phenitec Semiconductor. The chip was made through a shuttle service, in which multiple designs from different people share a single wafer to cut costs. On this wafer, one area belonged to the ISHI-kai and another was used by a different company. The idea is to pack as many designs as possible onto one wafer so prototypes can be made economically.
This chip was part of a 2025 shuttle. Design data was due in August and finished chips arrived around the end of December, roughly four months in total. Ichiken says the chip showed up just as they had almost forgotten about it.
Ichiken found the cost much lower than they expected. Twenty bare chips cost 210,000 yen. Adding the option to assemble them in LQFP packages brought the total to 300,000 yen. Because the chip also holds circuits designed by other people, splitting the cost among participants brings it down to tens of thousands of yen per person. Ichiken also mentions that manufacturing costs for this run were covered by Sanken Electric. With free open-source design tools as well, they feel the barrier to producing an original chip has come down considerably. The process node is 0.6 μm, which they believe is sufficient for analog semiconductors like this op-amp. They also note that this foundry is not the only one running domestic shuttle services like this.
Inspecting the Chip
Ichiken received both bare chips and packaged versions. The packaged ones look just like an ordinary IC. The bare chip is too small to see much with a camera, so they examined it under a microscope. The die holds circuits from other contributors alongside Ichiken's own. The IC's pin count is fixed and pins were divided among everyone, so some circuits had too few pins and are not connected to the lead frame at all. The ISHI-kai and Sanken Electric logos sit in the middle, and Ichiken's op-amp is in the upper left. Ichiken believes it was manufactured exactly as designed.
Test Setup
For testing, the IC went into a clamshell-type socket jig, with the circuit built on a breadboard. The relevant pins are:
- power supply pins
- a pin for attaching an external phase-compensation capacitor
- a dedicated VDD terminal for Ichiken's circuit
- terminals for the current source and the current mirror
- the op-amp inputs and output
The current source and current mirror have separate pins, and for this test they are shorted together. The separation is a fallback: if the on-chip current source doesn't work, current can be supplied from outside so the op-amp can still run.
First Test: Buffer Operation and Current Consumption
The first circuit was a voltage buffer running from a 5 V supply. The op-amp is single-supply, so the AC input was centered at 2.5 V, half the supply, with an amplitude of 1 V peak-to-peak. When power was applied, the output (red trace) tracked the input (yellow trace), and the op-amp worked. The video also includes footage of a measurement session held with the people who helped with the design.
Ichiken measured current consumption at 0.15 mA, which they consider quite low. For comparison they cite the NJM3404, a single-supply op-amp sold at shops such as Akizuki, whose current consumption they give as 2 mA. Even if their op-amp can't match its performance, they call the result reasonable.
Output Swing
Next Ichiken increased the input amplitude, keeping it centered at 2.5 V, to find where the output clips. Clipping began at about 4 V peak-to-peak input, with a maximum output of about 4.4 V. The top of the waveform clipped first, while the bottom held all the way down to 0 V.
Frequency Behavior and Slew Rate
Starting from 1 kHz, Ichiken raised the input frequency. At 10 kHz and 100 kHz the waveform showed no distortion. At 200 kHz the top began to distort. At 300 kHz the output became almost a triangle wave, which Ichiken attributes to a slew-rate limitation. Sweeping back down from 300 kHz toward 10 kHz, they concluded the op-amp is usable up to about 200 kHz. At that frequency the peaks are slightly distorted, which they consider acceptable.
Square-Wave Response and Phase Compensation
With a square-wave input, the output showed some ringing. A phase-compensation capacitor is built into the chip, and this was the part Ichiken felt worked "pretty well." Because the design also brings out a pin for an external capacitor, compensation can be strengthened further. Adding an external capacitor of about 10 pF greatly reduced the ringing, and removing it brought the ringing back.
Non-Inverting and Inverting Amplifiers
Configured as a non-inverting amplifier with a gain of two, the op-amp amplified the input as expected. As the input grew, the positive peaks began to clip, with output clipping at about 3.2 V. Ichiken takes this to mean the internal design still falls short in this area.
As an inverting amplifier, the circuit also inverted and amplified correctly. Past a certain amplitude, though, the output no longer reached the expected size and began to clip. Once the input exceeded 2.9 V, the output waveform was already wrong.
Load Drive
Finally Ichiken tested how much load the op-amp could drive, attaching resistive loads to the buffer circuit. It could not drive 10 kΩ. They explain that the output buffer inside this op-amp was not strengthened, so heavy loads are beyond it. Driving heavy loads would require adding a buffer stage after the output during design. Even an 80 kΩ load distorted the output, so Ichiken concludes it can only drive very light loads. With a smaller input amplitude it could handle somewhat heavier loads, but 10 kΩ still did not work.
Lessons: Layout Consumes Unlimited Time
Ichiken's conclusion is that the op-amp was designed and fabricated at the chip level and works as an op-amp without problems. The biggest lesson was how much time design and especially layout demand. They describe time "melting away" during layout. A connection drawn simply on a schematic can be placed and routed in many ways at the transistor level, and it is not clear whether a given arrangement will perform well, or which arrangement will best resist the effects of the foundry's process. Layout techniques that don't appear on the schematic at all add even more work, and in their words no amount of time is enough.
Fabrication runs have fixed deadlines, so when time runs short a layout may have to go to production with some compromises. Ichiken suspects this also happens in real industry. Some parts of their own layout got less attention than they wanted and ended up compromised to a degree. Even so, the chip worked as an op-amp. For viewers interested in semiconductor design and layout, Ichiken points to the documentation linked in the video description.
Hello. Today, I built my own operational amplifier starting with semiconductor circuits. I'll introduce the process of making it and verify that the op-amp I actually built works well.
This is the silicon chip for the operational amplifier that I actually made. Transistors are made on this chip and wired together on the chip. I previously built an operational amplifier using discrete transistor components. Today, we'll do something like an upgraded version of that. First, we'll show you how to design an operational amplifier at the transistor level on this silicon chip.
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First, we'll follow an overview and timeline of the design. Design began around June 2025. The deadline for submitting design data was in early August. Therefore, I studied operational amplifier design, how to use the software, and semiconductor layout at a fairly rapid pace.
In designing the op-amp circuit for this project, I received a lot of support from ISHI-KAI, an open-source semiconductor community. Information about ISHI-KAI's activities and the semiconductor design methods they offer is collected in the description. Please check it out if you're interested. It's difficult to introduce everything I did in designing this op-amp in this video, so I'll introduce only the important parts as we go along.
The basic design process is to draw a schematic, simulate it, draw the layout, and verify the layout. It's much the same as electronic circuit design. If you've used the circuit simulator LTspice or drawn a circuit in the circuit CAD program KiCad, I'm sure you can also design and lay out a simple op-amp circuit. Some aspects of learning how to use this software can be a little difficult. If you're doing this for the first time, I think starting with a logic NOT circuit will let you move forward without getting stuck.
Next, we'll touch on the software used to design semiconductors. Such software is generally not cheap. However, open-source simulators and layout software are available free of charge. Volunteers have put things together to make the software easy to set up. Process design kits, called PDKs, which are also required for semiconductor design, are available as well. I'm very thankful for that. The environment can be set up easily. The actual procedure and other details are in the description, so please check there.
Here is the actual circuit design. When designing circuits using discrete semiconductors, the performance of the component itself is fixed, and you make adjustments using external resistors and so on. But in transistor-level design, you can set the performance of the transistor itself. This gives you quite a lot of design freedom.
More freedom sounds good, but for a beginner like me, it actually makes things more difficult, because I don't know what transistor performance to set. This time, I learned a lot from the ISHI-KAI members as I went along, including approximately what values would make a good design. I think you could do something similar using the PDF documents in the description.
This design uses a CMOS process. PMOS has lower performance than NMOS. To get the same level of performance from PMOS, you need about twice the area of NMOS. I'll show you this in the layout design later. When using discrete components, you can use a complementary pair, so there aren't many situations where you're that aware of the difference in performance. When designing at a lower level like this, you need to think about these things too.
Here is the circuit we designed. Breaking it down into blocks, this part is the input differential amplifier circuit, this is the output section, and this is the reference current source. In the actual design process, you separate the circuit into small blocks and create test benches. If all the circuits work well in their test benches, you put them together, simulate them, and make sure they work without problems.
Once you've made it this far, the next step is transistor layout design. Designing this project made me realize how much depth there is to transistor layout. I'll introduce a few things we worked on and some important points. Here is the finished layout. You probably can't tell much from a quick glance, but I worked quite hard on this circuit. This part is the input differential amplifier circuit, this area is the reference current source, this part handles phase compensation and so on, and this part is the output circuit.
I'll show you what we did. Let's look at the differential amplifier circuit here. It has a point-symmetric structure. This is a layout technique called common centroid. For FETs used in pairs, as in a differential amplifier circuit, arranging them with point symmetry helps prevent temperature differences between transistors A and B shown here. This gives you better temperature characteristics.
Next is dummy polysilicon. This concerns the semiconductor manufacturing process. Apparently, the silicon at the ends gets scraped away during manufacturing. If the transistor gets scraped away, the circuit will deviate from its designed characteristics. Therefore, by placing additional transistors at the ends that don't contribute to circuit operation, you can protect the transistors that affect the operation of the internal circuitry.
Next are double vias and double contacts. Vias and contacts have higher resistance than wiring, so adding multiple vias and contacts lowers the resistance. These structures are also very fine, and a via or contact may fail because of manufacturing defects. Making multiple vias and contacts helps counter this, allowing the circuit to work even if a defect occurs. We often use multiple vias on printed circuit boards to lower resistance. It's the same thing. We also make the wiring that carries current thicker overall.
Once you have the layout, you need to verify that it matches the schematic and doesn't violate any design rules. If the layout is incorrect or violates the design rules, you may have to delete something you spent a lot of time creating and start over from the beginning. This is quite time-consuming. The circuit design didn't take that long. Layout design and verification took the longest. I think I spent about 30 hours on them.
When the layout is finished, you give the data to a semiconductor foundry and have a chip made. This time, I had it made by Phenitec Semiconductor. They offer what's called a shuttle service, where your chips share a wafer with other people's chips to make manufacturing cheaper. For example, this part of the wafer is for ISHI-KAI, and this other area is used by another company. You pack as much as possible onto one wafer to make prototype chips economically.
The chip we prototyped was made on a shuttle run in 2025. That year, the deadline for submitting design data was in August, and the finished chips arrived around the end of December. It took roughly four months for the chips to be completed.
As for the price, it was cheaper than I expected. It costs 210,000 yen for 20 bare chips. Including the assembly option to put them in LQFP packages, the total is 300,000 yen. I thought making semiconductor chips would cost more, so it was much cheaper than I had imagined. This time, circuits designed by other people also share a single chip. Dividing the cost among those people brings the cost per person down to tens of thousands of yen. Sanken Electric covered the manufacturing cost this time.
The design can also be done for free using open-source software. I feel the barrier to making an original chip has dropped quite a bit. The process node is 0.6 μm, which I think is fine for making an analog semiconductor like the operational amplifier designed for this project. This isn't the only foundry offering domestic shuttle runs like these. If you're interested, look for them.
Four months later, we received the manufactured chips. They arrived around the time I'd almost forgotten about them. I received both bare chips and packaged chips. The packaged ones look just like ordinary ICs. On the left is a bare chip. This is about as much as you can see by zooming in with the camera. It's too small, so let's observe it with a microscope.
Here is an overall view of the chip. It contains not only the circuit Ichiken built, but circuits made by other people as well. The number of IC pins is fixed, so we divide them among everyone. There weren't enough pins to connect all the circuitry on the chip to the lead frame, so some circuits aren't connected. The ISHI-KAI and Sanken Electric logos are in the middle. Here in the upper-left corner is the circuit designed by Ichiken. I believe it was manufactured exactly as designed. You can find the other people's circuits through the GitHub link in the description. Please check there.
Now, we'll check whether the op-amp I built works. We have a clamshell-type jig like this. I put the IC chip in it and built the circuit on a breadboard. The correspondence between the IC pins and the actual contents looks like this. This area is the power supply, this is where the external phase compensation capacitor connects, and VDD is the terminal for my dedicated power supply.
These are the terminals for the current source and current mirror. Since the current source is made inside the chip this time, we're shorting these together. The reason they're separate is so that, if the current source inside the chip doesn't work, we can supply current externally to make it work. The bottom two are the operational amplifier inputs, and this is the operational amplifier output.
First, I'll create a buffer circuit like this and try running it. The power supply is 5 V. The op-amp we built uses a single supply, so we'll input an AC voltage centered at half the supply voltage, or 2.5 V. Let's actually run it. First, let's look at just the input signal. This is a 1 V peak-to-peak input signal centered at 2.5 V. Then we turn on the op-amp.
Good. It's working. The yellow waveform above is the input voltage, and the red waveform below is the operational amplifier's output voltage.
I'm filming it now, but we actually held a measurement session. The people who helped design and make this op-amp gathered for the session. Here's what happened then.
The operational amplifier's current consumption is 0.15 mA. I think that's quite low. The NJM3404 single-supply operational amplifier sold at Akizuki and other places consumes 2 mA, so compared with that, the current consumption is quite low. Even if it can't match the performance, it's reasonably good.
From here, we'll change the input signal and see how well it performs. First, let's increase the input voltage amplitude. As we increase it, the output waveform should start clipping at some point. With the input voltage centered at 2.5 V, it started clipping at about 4 V peak-to-peak. The maximum output voltage is about 4.4 V. The top of the waveform started clipping first. The bottom is still harder to clip; it reaches 0 V. The top starts clipping first.
Next, we'll look at higher frequencies. It's currently 1 kHz. We'll set it to 10 kHz. The waveform doesn't appear distorted yet. It looks fine. Now let's set the frequency to 100 kHz. What do you think? It still looks fine to me. The waveform isn't distorted.
Let's raise the frequency further. At 200 kHz, the top is distorted. At 300 kHz, it's no good. I think this is a slew-rate issue. The waveform looks like a triangular wave. Let's see what the practical frequency range is. Lowering the frequency from 300 kHz in 10 kHz steps, I get the impression it can be used up to about 200 kHz. The waveform is slightly distorted at the peak, but I think it's acceptable.
Next, we're looking at the output waveform with a square-wave input. There is some ringing like this. The phase compensation capacitor has quite an effect here. I've built a phase compensation capacitor inside, but adding an external capacitor can increase the phase compensation further. For example, adding an external capacitor of about 10 pF gives a waveform like this. You can see that the ringing is much reduced. It looks like this, and when you remove it, it goes like this.
Next, we'll try making a non-inverting amplifier circuit like this. Here it is in operation. The amplitude is amplified by a factor of two. It seems to be working fine. As we increase the input voltage, though, once the amplitude reaches a certain point, the positive peak starts clipping. I guess the internal design isn't quite there yet. Looking at it here, the output voltage clips at about 3.2 V.
Next, let's run the inverting amplifier circuit shown here. It's running now, and proper inverting amplification is achieved. As we increase the input voltage amplitude, it continues to amplify. But if you increase it beyond a certain point, it doesn't get as large as it should, and the waveform clips. When the input voltage exceeds 2.9 V, the output voltage waveform is already wrong.
Next, let's see how much load it can drive. We'll use this buffer circuit to try driving a resistive load. Let's try 10 kΩ first. No. This is because we haven't strengthened the op-amp's internal output buffer, so it can't drive heavy loads. If you want to drive heavy loads, during the design stage, the outputs are placed at the rear of the…
We need to add buffer circuitry. So how much load can it really drive? Right now, it's driving an 80 kΩ load. This still distorts the output waveform, so it looks like we can only drive a very light load.
Incidentally, as the input amplitude is reduced, it seems to be able to drive slightly heavier loads. Still, it cannot drive about 10 kΩ.
So today we designed and manufactured an operational amplifier at the semiconductor chip level, and I've checked that the resulting op-amp circuit works without problems.
When it came time to make it, I found that design and layout required a lot of time. Especially with the layout, time just melts away. For example, the schematic shows a connection, but in the transistor layout, I'm not sure whether placing and connecting them this way will give better performance, or whether we should do it another way to make the layout less susceptible to the effects of the foundry's process. Then there are layout techniques that aren't shown on the schematic. If you try to do all of these things, no amount of time is enough for the transistor layout.
Semiconductor designs like these have deadlines to meet. If you need more time, you may have to submit a layout with some compromises for production. Perhaps that happens in actual business. In the layout we did this time, there were some areas that I just couldn't devote enough time to, so I made some compromises in those areas. Ultimately, it was working fine as an operational amplifier.
If you are interested in semiconductor design and layout, I've linked a document explaining how to do it in the description. Please check it out!
If you found this video helpful, please give it a like. If you have any concerns, please let us know in the comments! Thank you for watching the video until the end.
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